Bias-temperature instabilities in silicon carbide MOS devices


We have investigated bias-temperature instabilities (BTIs) in 4H-SiC transistors and capacitors under a range of stress conditions. The threshold voltage V TH of nMOS transistors decreases for elevated temperature stress under negative bias, when the surface is accumulated. Devices stressed with the surface inverted do not exhibit significant V TH shifts. Similar results are observed for nMOS and pMOS capacitors stressed in accumulation (measurable shift) or inversion (no significant shift). V TH shifts due to BTI stressed under negative bias correlate strongly with the additional ionization of deep dopants in SiC at elevated temperatures. The charge that leads to BTI lies in interface traps that are more than 0.6 eV below the SiC conduction band, nitrogen-related defects, and O vacancies in the SiO2.

Publication Title

Bias Temperature Instability for Devices and Circuits