Multi-stacked 1G cell/layer pipe-shaped BiCS flash memory

Authors

• Takashi Maeda, Toshiba Corporation
• Kiyotaro Itagaki, Toshiba Corporation
• Tomoo Hishida, Toshiba Corporation
• Ryota Katsumata, Toshiba Corporation
• Masaru Kito, Toshiba Corporation
• Yoshiaki Fukuzumi, Toshiba Corporation
• Masaru Kido, Toshiba Corporation
• Hiroyasu Tanaka, Toshiba Corporation
• Yosuke Komori, Toshiba Corporation
• Megumi Ishiduki, Toshiba Corporation
• Junya Matsunami, Toshiba Corporation
• Tomoko Fujiwara, Toshiba Corporation
• Hideaki Aochi, Toshiba Corporation
• Yoshihisa Iwata, Toshiba Corporation
• Yohji Watanabe, Toshiba Corporation

Abstract

A three-dimensional 16 stacked 1G cell/layer Pipe-shaped Bit-Cost Scalable (P-BiCS) flash memory test chip with 60nm technology has been developed. The effective 1-bit cell size is 0.00082 um2. This paper describes the branched control gate configuration and the new erase operation which are suitable for P-BiCS flash memory. P-BiCS flash memory is one of the most promising candidates for realizing the future T-bit storage device.

Publication Title

IEEE Symposium on VLSI Circuits Digest of Technical Papers

Recommended Citation

Maeda, T., Itagaki, K., Hishida, T., Katsumata, R., Kito, M., Fukuzumi, Y., Kido, M., Tanaka, H., Komori, Y., Ishiduki, M., Matsunami, J., Fujiwara, T., Aochi, H., Iwata, Y., & Watanabe, Y. (2009). Multi-stacked 1G cell/layer pipe-shaped BiCS flash memory. IEEE Symposium on VLSI Circuits Digest of Technical Papers, 22-23. Retrieved from https://digitalcommons.memphis.edu/facpub2/658