4.48-GHz Fractional-N Frequency Synthesizer with Spurious-Tone Suppression via Probability Mass Redistribution
Abstract
A 4.48-GHz type-II charge pump fractional- {N} PLL implemented in a 0.18- μ \text{m} BiCMOS process is presented. The divider controller's output is processed using a novel block, the probability mass redistributor, which statistically reconfigures the modulation noise such that fractional spurs are minimized. Measurements demonstrate in-band fractional spurs of -80 dBc. The solution, which is a drop-in modification of a conventional MASH structure, incurs a modulator area increase of 22%, and can be used in conjunction with other linearization strategies.
Publication Title
IEEE Solid-State Circuits Letters
Recommended Citation
Donnelly, Y., Keaveney, M., Kennedy, M., Breslin, J., Tulisi, S., Patil, S., Curtin, C., Brookes, S., Shelly, B., & Griffin, P. (2019). 4.48-GHz Fractional-N Frequency Synthesizer with Spurious-Tone Suppression via Probability Mass Redistribution. IEEE Solid-State Circuits Letters, 2 (11), 264-267. https://doi.org/10.1109/LSSC.2019.2943936
