Architectures for maximum-sequence-length digital delta-sigma modulators
Abstract
In this paper, we extend the idea developed in some of our earlier works of using output feedback to make the quantization step in a digital delta-sigma modulator (DDSM) appear prime. This maximizes the cycle lengths for constant inputs, spreading the quantization error over the maximum number of frequency terms, and consequently, minimizing the power per tone. We show how this concept can be applied to multibit higher order error-feedback modulators (EFMs). In addition, we show that the idea can be implemented in a class of single-quantizer DDSMs (SQ-DDSM) where STF (z)=z-L and NTF (z)=(1-z-1) L. © 2008 IEEE.
Publication Title
IEEE Transactions on Circuits and Systems II: Express Briefs
Recommended Citation
Hosseini, K., & Kennedy, M. (2008). Architectures for maximum-sequence-length digital delta-sigma modulators. IEEE Transactions on Circuits and Systems II: Express Briefs, 55 (11), 1104-1108. https://doi.org/10.1109/TCSII.2008.2004537
