Modeling and simulation of ΔΣ fractional-N pll frequency synthesizer in Verilog-AMS
Abstract
A Verilog-AMS model of a fractional-N frequency synthesizer is presented that is capable of predicting spurious tones as well as noise and jitter performance. The model is based on a voltage-domain behavioral simulation. Simulation efficiency is improved by merging the voltage controlled oscillator (VCO) and the frequency divider. Due to the benefits of Verilog-AMS, the ΔΣ modulator which is incorporated in the synthesizer is modeled in a fully digital way. This makes it accurate enough to evaluate how the performance of the frequency synthesizer is affected by cyclic behavior in the ΔΣ modulator. The spur-minimizing effect of an odd initial condition on the first accumulator of the ΔΣ modulator is verified. Sequence length control and its effect on the fractional-N frequency synthesizer are also discussed. The simulated results are in agreement with prior published data on fractional-N synthesizers and with new measurement results. Copyright © 2007 The Institute of Electronics, Information and Communication Engineers.
Publication Title
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Recommended Citation
Zhipeng, Y., Wenbin, C., & Michael Peter, K. (2007). Modeling and simulation of ΔΣ fractional-N pll frequency synthesizer in Verilog-AMS. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E90-A (10), 2141-2147. https://doi.org/10.1093/ietfec/e90-a.10.2141
