Performance analysis of low power high speed pipelined adders for digital ΣΔ modulators
Abstract
The carry skip adder (CSA) is widely assumed to outperform the carry lookahead adder (CLA) in terms of power and area. However, for pipelined adders used in digital ΣΔ modulators (DDSM), it is shown that the CLA has similar performance to the CSA architecture when low bit blocks are used. Furthermore, the CSA outperforms the CLA in terms of glitch content and hence the CSA is more suitable for the operational frequencies of DDSMs. © The Institution of Engineering and Technology 2006.
Publication Title
Electronics Letters
Recommended Citation
Bhansali, P., Hosseini, K., & Kennedy, M. (2006). Performance analysis of low power high speed pipelined adders for digital ΣΔ modulators. Electronics Letters, 42 (25), 1442-1444. https://doi.org/10.1049/el:20062394
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