Performance limits for open-loop fractional dividers
Abstract
The architecture of an Open-loop fractional divider is presented comparing the performance using different orders of DDSM to implement the Phase Error Calculator block. We show that the performance of the output clock is unconnected from the order of the DDSM and that consequently the first order structure is the most suitable for the implementation in a real device.
Publication Title
2017 28th Irish Signals and Systems Conference, ISSC 2017
Recommended Citation
Tulisi, S., & Kennedy, M. (2017). Performance limits for open-loop fractional dividers. 2017 28th Irish Signals and Systems Conference, ISSC 2017 https://doi.org/10.1109/ISSC.2017.7983612
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