Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs
Abstract
Fractional-N digital phase-locked loops (DPLL's) typically use a multi-stage noise-shaping (MASH) digital Δ-Σ modulator (DDSM) divider controller to synthesize an output frequency that is a non-integer multiple of the reference. The quantization error (QE) arising from the divider controller, if not being canceled prior to reaching the time-to-digital converter (TDC), can overwhelm the TDC input jitter level and in turn deteriorate the phase noise (PN) of the TDC, and hence that of the DPLL at the system level. This sets a performance limit for such DPLLs, for which case it is crucial to predict explicitly the worst-case output PN in order to analyze fractional-N PN mitigation techniques critically. This paper investigates this scenario, for which the input jitter analysis and output PN prediction are performed. Multi-rate discrete-time behavioral simulation at the system level confirms the accuracy of our analytical predictions.
Publication Title
PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings
Recommended Citation
Wang, X., & Kennedy, M. (2023). Performance Limits of Fractional-N Digital PLLs with Mid-Rise TDCs. PRIME 2023 - 18th International Conference on Ph.D Research in Microelectronics and Electronics, Proceedings, 317-320. https://doi.org/10.1109/PRIME58259.2023.10161782
