Mechanism of phosphorus passivation of near-interface oxide traps in 4H-SiC MOS devices investigated by CCDLTS and DFT calculation
Abstract
Interfacial charge trapping in 4H-SiC MOS capacitors with P doped SiO2 or phospho-silicate glass (PSG) as a gate dielectric has been investigated with temperature dependent capacitance-voltage measurements and constant capacitance deep level transient spectroscopy (CCDLTS) measurements. The measurements indicate that P doping in the dielectric results in significant reduction of near-interface electron traps that have energy levels within 0.5 eV of the 4H-SiC conduction band edge. Extracted trap densities confirm that the phosphorus induced near-interface trap reduction is significantly more effective than interfacial nitridation, which is typically used for 4H-SiC MOSFET processing. The CCDLTS measurements reveal that the two broad near-interface trap peaks, named 'O1' and 'O2', with activation energies around 0.15 eV and 0.4 eV below the 4H-SiC conduction band that are typically observed in thermal oxides on 4H-SiC, are also present in PSG devices. Previous atomic scale ab initio calculations suggested these O1 and O2 traps to be carbon dimers substituted for oxygen dimers (CO=CO) and interstitial Si (Sii) in SiO2, respectively. Theoretical considerations in this work suggest that the presence of P in the near-interfacial region reduces the stability of the CO=CO defects and reduces the density of Sii defects through the network restructuring. Qualitative comparison of results in this work and reported work suggest that the O1 and O2 traps in SiO2/4H-SiC MOS system negatively impact channel mobility in 4H-SiC MOSFETs.
Publication Title
Semiconductor Science and Technology
Recommended Citation
Jayawardena, A., Shen, X., Mooney, P., & Dhar, S. (2018). Mechanism of phosphorus passivation of near-interface oxide traps in 4H-SiC MOS devices investigated by CCDLTS and DFT calculation. Semiconductor Science and Technology, 33 (6) https://doi.org/10.1088/1361-6641/aabda2
