Design methodology for a dithered reduced complexity digital MASH delta-sigma modulator
Abstract
Two classes of techniques have been developed to whiten the quantization noise in Digital Delta-Sigma Modulators: deterministic and stochastic. A reduced complexity Multi-stAge noise SHaping (MASH) DDSM designed with the deterministic technique was proposed in [1] and its design methodology was presented in [2]. Rules for selecting the wordlengths of each stage for the RC MASH DDSM using the stochastic technique are presented in this paper. We show that the RC MASH DDSMs can not only be designed with the deterministic technique [2], but they can achieve similar performance with up to 30% less hardware, compared with the conventional DDSM, when designed using the stochastic technique with our methodology. © 2008 IEEE.
Publication Title
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Recommended Citation
Ye, Z., & Kennedy, M. (2008). Design methodology for a dithered reduced complexity digital MASH delta-sigma modulator. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, 426-429. https://doi.org/10.1109/ICECS.2008.4674881
