Design methodology for a reduced complexity single quantizer digital delta-sigma modulator
Abstract
Digital delta-sigma modulators (DDSMs) usually belong to one of two classes called Multi-stAge noise SHaping (MASH) DDSMs and Single-Quantizer (SQ) DDSMs [1]. A reduced complexity (RC) MASH DDSM was proposed in [2] and its design methodology was presented in [3]. In this paper, we apply a similar design strategy to the SQ-DDSM. We show that the RC SQ-DDSM can achieve similar performance but with nearly 20% less hardware compared with the conventional SQ DDSM, when designed with our methodology. © 2008 IEEE.
Publication Title
Proceedings of the International Conference on Microelectronics, ICM
Recommended Citation
Ye, Z., & Kennedy, M. (2008). Design methodology for a reduced complexity single quantizer digital delta-sigma modulator. Proceedings of the International Conference on Microelectronics, ICM, 48-51. https://doi.org/10.1109/ICM.2008.5393776
