Hardware reduction in delta-sigma digital-to-analog converters via bus-splitting

Authors

Brian Fitzgibbon, Tyndall National Institute
Michael Peter Kennedy, Tyndall National InstituteFollow
Franco Maloberti, Università degli Studi di Pavia

Abstract

This paper discusses a bus-splitting technique for hardware reduction in error feedback digital delta-sigma modulators (DDSMs). The technique is based on error masking and is applied to DDSMs with sinusoidal inputs. We consider the components that contribute to the output signal-to-noise ratio in conventional DDSMs and review new architectures for implementing the digital algorithms without sacrificing performance.

Publication Title

IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum

Recommended Citation

Fitzgibbon, B., Kennedy, M., & Maloberti, F. (2011). Hardware reduction in delta-sigma digital-to-analog converters via bus-splitting. IMEKO TC4 International Workshop on ADC Modelling, Testing and Data Converter Analysis and Design 2011, IWADC 2011 and IEEE 2011 ADC Forum, 120-125. Retrieved from https://digitalcommons.memphis.edu/facpubs/17480