Hardware reduction in digital delta-sigma modulators via bus-splitting and error maskingpart I: Constant input
Abstract
In this two-part paper, a design methodology for bus-splitting digital delta-sigma modulators (DDSMs) is presented. The design methodology is based on error masking and is applied to both ditherless and dithered DDSMs with constant and sinusoidal inputs. Rules for selecting the appropriate wordlengths of the constituent DDSMs are derived which ensure that the spectral performance of the bus-splitting architecture is comparable to that of the conventional design but with less hardware. Behavioral simulations and experimental results confirm the theoretical predictions. Part I addresses ditherless MASH DDSMs with constant inputs; Part II focuses on DDSMs with dither and sinusoidal inputs. © 2011 IEEE.
Publication Title
IEEE Transactions on Circuits and Systems I: Regular Papers
Recommended Citation
Fitzgibbon, B., Kennedy, M., & Maloberti, F. (2011). Hardware reduction in digital delta-sigma modulators via bus-splitting and error maskingpart I: Constant input. IEEE Transactions on Circuits and Systems I: Regular Papers, 58 (9), 2137-2148. https://doi.org/10.1109/TCSI.2011.2112890
