Hardware reduction in digital delta-sigma modulators via error masking - Part I: MASH DDSM
Abstract
Two classes of techniques have been developed to whiten the quantization noise in digital delta-sigma modulators (DDSMs): deterministic and stochastic. In this two-part paper, a design methodology for reduced-complexity DDSMs is presented. The design methodology is based on error masking. Rules for selecting the word lengths of the stages in multistage architectures are presented. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation and experimental results confirm theoretical predictions. Part I addresses MultistAge noise SHaping (MASH) DDSMs; Part II focuses on single-quantizer DDSMs. © 2009 IEEE.
Publication Title
IEEE Transactions on Circuits and Systems I: Regular Papers
Recommended Citation
Ye, Z., & Kennedy, M. (2009). Hardware reduction in digital delta-sigma modulators via error masking - Part I: MASH DDSM. IEEE Transactions on Circuits and Systems I: Regular Papers, 56 (4), 714-726. https://doi.org/10.1109/TCSI.2008.2003383
