Hardware reduction in digital delta-sigma modulators via error masking - Part II: SQ-DDSM
Abstract
In this two-part paper, a design methodology for reduced-complexity digital delta-sigma modulators (DDSMs) based on error masking is presented. Rules for selecting the wordlengths of the stages in multistage architectures are elaborated. We show that the hardware requirement can be reduced by up to 20% compared with a conventional design, without sacrificing performance. Simulation results confirm theoretical predictions. Part I addresses multistage noise-shaping DDSMs, whereas Part II focuses on single-quantizer DDSMs. © 2009 IEEE.
Publication Title
IEEE Transactions on Circuits and Systems II: Express Briefs
Recommended Citation
Ye, Z., & Kennedy, M. (2009). Hardware reduction in digital delta-sigma modulators via error masking - Part II: SQ-DDSM. IEEE Transactions on Circuits and Systems II: Express Briefs, 56 (2), 112-116. https://doi.org/10.1109/TCSII.2008.2010188
